FIG. 1 is a cross-sectional view of a Schottky gate field effect transistor (hereinafter referred to as MESFET) which is shown as a first example of conventional field effect transistors. In FIG. 1, on a semi-insulating semiconductor substrate 1 of, for example, GaAs, a high-resistivity buffer layer 2 is disposed, and an n-type channel layer 3 doped with, for example, Si is disposed on the high-resistivity buffer layer 2. A gate electrode 4 is disposed on the n-type channel layer 3, with n.sup.+ -type contact layers 51 and 52 disposed on the opposite sides of the gate electrode 4. A source electrode 6 is disposed on the n.sup.+ -type contact layer 51, and a drain electrode 7 is disposed on the n.sup.+ -type contact layer 52,
Another example of conventional field effect transistors is shown in FIG. 2, which is a cross-sectional view of a heterojunction field effect transistor (HFET). As in the case of MESFET shown in FIG. 1, the HFET of FIG. 2 includes a semi-insulating semiconductor substrate 1 of, for example, GaAs, and a high-resistivity buffer layer 2 disposed on the substrate 1. Different from the MESFET of FIG. 1, however, an undoped channel layer 32 is disposed on the high-resistivity buffer layer 2. For example, a Si-doped n.sup.+ -type electron supply layer 8 is disposed on the undoped channel layer 3, and an n.sup.+ -type contact layer 5 is disposed on the electron supply layer 8.
A broken line 33 shown passing through the undoped channel layer 32 in FIG. 2 denotes a two-dimensional electron gas formed by electrons which are supplied from the large bandgap, small electron-affinity n.sup.+ -type electron supply layer 8 to the channel layer 32 having a small bandgap relative to that of the layer 8 and having a large electron-affinity, and confined in a potential well in the channel layer 32 due to quantum mechanical effects. In a central portion of the n.sup.+ -type contact layer 5, a recess 9 is formed, and a gate electrode 4 is disposed in the recess 9. On the n.sup.+ -type contact layer 5, a source electrode 6 and a drain electrode 7 are disposed on the opposite sides of the gate electrode 4.
Under a normal biasing condition, each of the MESFET in FIG. 1 and the HFET in FIG. 2 has its source electrode 6 grounded and has its drain electrode 7 supplied with a positive bias voltage V.sub.d. Under such a condition, the speed of electrons supplied from the source to the channel region immediately beneath the gate is dependent on a potential V.sub.1 at the source side of the channel region 31. The potential V.sub.1 is dependent on a drain current I.sub.d, which is the result of drifting of electrons caused by the potential V.sub.d at the drain electrode 7, and on a parasitic resistance R.sub.s between the source electrode 6 and the source side of the channel region 31, i.e. V.sub.1 =I.sub.d .times.R.sub.s. In an ordinary FET in which the width of a gate electrode is on the order of 200 .mu.m, the drain current I.sub.d and the parasitic resistance R.sub.s may be about 10 mA and about 2 Q, respectively, and, accordingly, the potential V.sub.1 may be about 0.02 V. This voltage is too low to accelerate electrons entering into the part beneath the gate. Thus, in conventional devices, the initial speed of electrons supplied to the channel region immediately beneath the gate is low, which makes it difficult to realize high speed MESFET operation.
In the HFET of FIG. 2, electrons are confined within a potential well in the channel layer 32, and the degree of freedom of electrons in the y direction is lost due to the hetero-barrier formed between the channel layer 32 and the n.sup.+ -type electron supply layer 8 so that scattering of electrons in the y direction will decrease and the operation speed may be more or less improved in comparison with the MESFET shown in FIG. 1. However, the operation speed attained is still insufficient.
The operation speed could be improved by increasing the potential V.sub.1 in the source side of the channel region 31 immediately beneath the gate for both the MESFET of FIG. 1 and the HFET of FIG. 2 so that the initial speed of electrons supplied to the channel increases. However, when I.sub.d and R.sub.s are increased in order to increase V.sub.1, lattice vibration are also increased, which results in an increase in thermal noise. Thus, the noise figure NF of the FET's is degraded. Furthermore, because electrons supplied to the channel have various energy levels, they are subjected to various scattering. Therefore it is difficult to realize FET's with a high initial electron velocity in the channel region immediately beneath the gate and with low noise.
FET's which can be operated at high speed include FET's disclosed in Japanese Unexamined Patent Publication No. SHO 63-318782 and Japanese Unexamined Patent Publication No. SHO 62-211963. These FET's take advantage of so-called resonant tunneling. The FET disclosed in Japanese Unexamined Patent Publication No. SHO 63-318782 is an MESFET, of which the drain current (I.sub.D) versus source-drain voltage (V.sub.DS) characteristic exhibits a negative resistance. The FET shown in Japanese Unexamined Patent Publication No. SHO 62-211963 is an HFET which exhibits a peak drain current I.sub.D when a particular gate voltage is applied.
Due to resonant tunneling, the FET's disclosed in the above-mentioned Japanese unexamined patent publications can operate at a more or less higher speed. However, a resonant tunneling diode (RTD) in the source electrode side which provides the resonant tunneling effect is disposed on the channel layer parallel to the channel, so that hot electrons supplied through the RTD into the channel have not only a component of motion in the x direction which is parallel to the channel but also a component in the y direction which is perpendicular to the channel. Accordingly, hot electrons supplied to the channel are scattered during their travel to the portion of the channel immediately beneath the gate, and, therefore, a sufficiently high speed cannot be attained.
As discussed above, because electrons injected into the channel of conventional FET's are subject to various scattering, the initial speed of electrons entering into the channel immediately beneath the gate is insufficient, which impedes increasing operation speed and reducing noise.
The object of the present invention is to provide a FET which can operate at a high speed and with low noise, by eliminating disadvantages discussed above.